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FEATURES Fully Compliant with Standard and Enhanced GSM Specification -11 dBm Input 1 dB Compression Point 0 dBm Input Third Order Intercept 10 dB SSB Noise Figure (50 ) DC-500 MHz RF and LO Bandwidths Linear IF Amplifier Linear-in-dB and Stable over Temperature Voltage Gain Control Quadrature Demodulator On-Board Phase-Locked Quadrature Oscillator Demodulates IFs from 5 MHz to 50 MHz Low Power 8 mA at Midgain 2 A Sleep Mode Operation 2.7 V to 5.5 V Operation Interfaces to AD7013, AD7015 and AD6421 Baseband Converters 20-Lead SSOP
GSM 3 V Receiver IF Subsystem AD6459
FUNCTIONAL BLOCK DIAGRAM
LO I RF BPF PLL Q GAIN CONTROL FREF
AD6459
GENERAL DESCRIPTION
The AD6459 is a 3 V, low power receiver IF subsystem for operation at input frequencies as high as 500 MHz and IFs from 5 MHz up to 50 MHz. It is optimized for operation in GSM, DCS1800 and PCS1900 receivers. It consists of a mixer, an IF amplifier, I and Q demodulators, a phase-locked quadrature oscillator, a precise AGC subsystem, and a biasing system with external power-down. The AD6459's low noise, high intercept mixer is a doublybalanced Gilbert-Cell type. It has a nominal -11 dBm inputreferred 1 dB compression point and a 0 dBm input-referred third-order intercept. The mixer section of the AD6459 also includes a local oscillator (LO) preamplifier, which lowers the required LO drive to -16 dBm. The gain control input accepts an external gain-control voltage input from an external AGC detector or a DAC. It provides an 80 dB gain range with 27 mV/dB gain scaling. The I and Q demodulators provide in-phase and quadrature baseband outputs to interface with Analog Devices' AD7013
(IS54, TETRA, MSAT) AD7015 and AD6421 (GSM, DCS1800, PCS1900) baseband converters. An on-board quadrature VCO that is externally phase-locked to the IF signal drives the I and Q demodulators. This locked reference signal is normally provided by an external VCTCXO under the control of the radio's digital processor. The AD6459 can also provide demodulation of N-PSK and N-QAM in many non-TDMA systems when used with external analog carrier recovery systems such as the Costas Loop. Finally, the VCO can be phase-locked to a frequency that is deliberately offset from the IF as in the case of a Beat-Frequency oscillator (BFO) resulting in the product detection of CW or SSB. The AD6459 uses supply voltages from 2.7 V to 5.5 V over the temperature range of -40C to +85C. Operation is enabled by a CMOS logical level; response time is typically < 80 s. When disabled, the standby current is reduced to 2 A. The AD6459 comes in a 20-pin shrink small outline (SSOP) surface mount package.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 (c) Analog Devices, Inc., 1996
AD6459-SPECIFICATIONS (@ T = +25 C, V = 3.0 V, GREF = 1.2 V, unless otherwise noted)
A P
Model Parameter DYNAMIC PERFORMANCE MIXER Maximum RF and LO Frequency AGC Conversion Gain Variation Input 1 dB Compression Point Input Third-Order Intercept SSB Noise Figure1 Mixer Output Bandwidth at MXOP IF AMPLIFIERS AGC Gain Variation Input Referred Noise Input Resistance Bandwidth I AND Q DEMODULATORS Demodulation Gain Output Voltage Range Output Voltage Common-Mode Level Output Offset Voltage Error in Quadrature Amplitude Match I/Q Output Bandwidth Output Resistance GAIN CONTROL Total Gain Control Range Control Voltage Range at GAIN Gain Scaling Gain Law Conformance Bias Current at GREF Input Resistance at GAIN PLL Frequency Range Phase Noise Acquisition Time Input Drive Level (FREF) POWER-DOWN INTERFACE Logical Threshold Input Current for Logical High Turn-On Response Time Turn-Off Response time Standby Current POWER SUPPLY Supply Range Supply Current OPERATING TEMPERATURE TMIN to TMAX
Conditions
Min
AD6459ARS Typ Max
Units
0.2 V < VGAIN < 2.25 V @ VGAIN = 0.2 V @ VGAIN = 0.2 V @ ZS = 50 , FRF = 240 MHz, FLO = 229.3 MHz at -16 dBm @ -3 dB 0.2 V < VGAIN <2.25 V AC Short Circuit Input @ VGAIN = 0.2 V @ -3 dB
500 -3 to +16 -11 0 10 80 -13 to +46 3 5 50 17
MHz dB dBm dBm dB MHz dB nV/Hz k MHz dB VP - 0.2 V V 150 mV 3.5 Degree dB MHz k dB V mV/dB dB A k MHz Degree rms s mV V A s s A 5.5 V mA C C
Differential, IRXP, IRXN, QRXP, QRXN (Not Power Supply Dependent) Differential, VGAIN = GREF Differential from I to Q, IF = 13 MHz I to Q CLOAD = 10 pF Each Pin Mixer + IF + Demod, 0.2 V < VGAIN <2.25 V
0.3 1.5 -150 1.5 0.25 2 4.7 76 0.2 23 27 0.5 0.5 20
2.4 32
5 IF = 19.5 MHz, Using Suggested Filter 100 Power Up on Logical High To Fully Meet Specifications (PLL Lock) To 200 A Supply Current 1.5 75 80 1 2 2.7 @ VGAIN = 1.2 V Operation to 3.3 V Minimum Supply Voltage Operation to 2.7 V Minimum Supply Voltage -40 -25 8 0.5 80
50
VPOS
+85 +85
NOTES 1 Including IF noise and using suggested filter, at V GAIN = 0.2 V. Specifications subject to change without notice.
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AD6459
ABSOLUTE MAXIMUM RATINGS 1 PIN CONNECTION
Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . +5.5 V Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . 600 mW Operating Temperature Range . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature, Soldering (60 sec) . . . . . . . . . . . . +300C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended rating conditions for extended periods may affect device reliability. 2 Thermal Characteristics: 20-lead SSOP package: JA = 126C/W.
20-Pin SSOP (RS-20)
FREF 1 COM1 2 PRUP 3 LOIP 4 RFLO 5
20 VPS1 19 FLTR 18 VPS2 17 IRXP
AD6459
16 IRXN
TOP VIEW RFHI 6 (Not to Scale) 15 QRXP COM2 7 GREF 8 MXOP 9 14 QRXN 13 GAIN 12 IFIM 11 IFIP
ORDERING GUIDE
MXOM 10
Model AD6459ARS
Temperature Range -25C to +85C for 2.7 V to 5.5 V -40C to +85C for 3.3 V to 5.5 V
Package Description 20-Pin Plastic SSOP
Package Option RS-20
PIN DESCRIPTIONS
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Pin Label FREF COM1 PRUP LOIP RFLO RFHI COM2 GREF MXOP MXOM IFIP IFIM GAIN QRXN QRXP IRXN IRXP VPS2 FLTR VPS1
Description Frequency Reference Input Common 1 Power Up Input Local Oscillator Input RF "Low" Input RF "High" Input Common 2 Gain Reference Input Mixer Output "Plus" Mixer Output "Minus" IF Input "Plus" IF Input "Minus" Gain Control Input Q Output "Negative" Q Output "Positive" I Output "Negative" I Output "Positive" VPOS Supply 2 PLL Loop Filter VPOS Supply 1
Function Demodulation LO Input. May either be 3 V CMOS input or >100 mV p-p. AC-coupled for lowest stand by current. Ground. CMOS Compatible Power-Up Control; <1.5 V = OFF, >1.5 V = ON. AC-Coupled LO Input. 50 mV p-p drive needed, 500 mV p-p max. Mixer Differential Input. AC-coupled. Mixer Differential Input. AC-coupled. Ground. High Impedance Input. Sets gain scaling, typically 1.2 V. Differential Output of the Mixer. See Figure 22. Differential Output of the Mixer. See Figure 22. Differential Input of Variable Gain Amplifier. AC-coupled. Differential Input of Variable Gain Amplifier. AC-coupled. 0.2 V-2.4 V Using 3 V Supply. Max gain at 0.2 V. Differential Q Output. Output resistance 4.7 k. Differential Q Output. Output resistance 4.7 k. Differential I Output. Output resistance 4.7 k. Differential I Output. Output resistance 4.7 k. Supply Voltage. Series RC Loop Filter. Connected to VPS2. Supply Voltage.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD6459 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD6459
R1 20k C12 1nF R9 50 PRUP C2 1nF LOIP RFHI R3 50 GREF C3 1nF R2 50 C4 1nF 1 FREF 2 COM1 3 PRUP 4 LOIP 5 RFLO 6 RFHI 7 COM2 8 GREF 9 MXOP VPOS OPEN R4 C5 1nF MXOP C13 10nF MXOM OPEN R5 10 MXOM VSP1 20 R8 1k FLTR 19 VSP2 18 C10 1nF C11 0.1F IRXP VPOS C1 0.1F VPOS FREF
AD6459
IRXP 17 IRXN 16 QRXP 15 QRXN 14 GAIN 13 IFIM 12 IFIP 11 C7 1nF R6 50 R7 50 IFIM C8 1nF C9 10nF (BOTTOM)
IRXN
QRXP
QRXN
GAIN
C6 1nF IFIP
Figure 1. AD6459 Characterization Board
1 VPOS 2 3 4 PRUP PRUP FREF VPOS IRXP IRXN VP 8 7 A=1 6 C4 0.1F C5 0.1F VN VP 8 7 A=1 6 C6 0.1F C7 0.1F VN VP R4 50 IOUT
FREF
AD830
VN 5
LOIP
LOIP
AD6459
CHARACTERIZATION BOARD
1 QRXP QRXN GAIN 2 3 4
VP
R3 50 IOUT
RFIP
RFIP
GREF
GREF MXOP MXOM IFIP
AD830
VN 5
IFIN
GAIN
1 2 3 4
VP 8 7 A=1 6 C3 0.1F C2 0.1F
VP
1 2 3
VP 8 7 A=1 6 C11 0.1F C10 0.1F
VP
R6 50
1 2 3
VP 8 7 A=1 6 C9 0.1F C8 0.1F
VP
R5 50
AD830
VN 5
VN
4
AD830
VN 5
VN
4
AD830
VN 5
VN
R2 50 MXOP IFIN
R1 50
Figure 2. Characterization Test Set
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20 18 16 SSB NF - dB RIN = 50, IF = 13MHz 14 12 10 -5 RIN = 400, IF = 13MHz 6 50 -10 100 150 200 250 300 RF FREQUENCY - dB 350 400 450 6 10 14 18 22 26 30 34 RF FREQUENCY - MHz 38 42 46 20 VGAIN = 0.2V 15
RIN = 50, F = 45MHz
GAIN - dB
10
VGAIN = 1.0V
RIN = 50, IF = 26MHz RIN = 1k, IF = 13MHz
5
0 VGAIN = 2.25V
8
Figure 3. Mixer Noise Figure vs. RF Frequency
Figure 6. Mixer Conversion Gain vs. IF Frequency, TA = +25C, VPOS = 2.7 V, VREF = 1.2 V, FRF = 250 MHz
2000 1800 1600 1400 RESISTANCE - 1200 1000 800 600 400 200 0 50 C SHUNT VGAIN = 2.2V 100 150 R SHUNT VGAIN = 0.2V 450 500 C SHUNT VGAIN = 1.0V R SHUNT VGAIN = 2.2V C SHUNT VGAIN = 0.2V
5.0 4.8 4.6 CAPACITANCE - pF 4.4 4.2 4.0 3.8 3.6 3.4
70 AMP/DEMOD, VPOS = 2.7V 60 AMP/DEMOD, VPOS = 5.5V 50
GAIN - dB
40 30 20 MIXER, VPOS = 2.7V
10 3.2 3.0 550
MIXER, VPOS = 5.5V
200 250 300 350 400 RF FREQUENCY - MHz
0 -50 -40 -30 -20 -10
0
10
20 30
40
50
60
70 80
90
TEMPERATURE - C
Figure 4. Mixer Input Impedance vs. RF Frequency, VPOS = 2.7 V, TA = +25C
Figure 7. Mixer Conversion Gain and IF Amplifier/ Demodulator Gain vs. Temperature, VGAIN = 0.2 V, VREF = 1.2 V , FIF = 26 MHz, FRF = 250 MHz
20
-9 VPOS = 5.5V TA = +85C
VGAIN = 0.2V
INPUT 1dB COMPRESSION POINT REFERED TO 50 - dBm
15
-10
10
-11
GAIN - dB
VGAIN = 1.0V 5
VPOS = 5.5V TA = +25C VPOS = 2.7V TA = +25C VPOS = 2.7V TA = -25C
-12
0
-13
-5
VGAIN = 2.25V
-14 VPOS = 5.5V TA = -45C 0 0.5 1 1.5 GAIN VOLTAGE - Volts 2 2.5
-10 50
-15
100 150 200 250 300 RF FREQUENCY - MHz 350 400 450
Figure 5. Mixer Conversion Gain vs. RF Frequency, TA = +25C, VPOS = 2.7 V, VREF = 1.2 V, FIF = 26 MHz
Figure 8. Mixer Input 1 dB Compression Point vs. VGAIN, VREF = 1.2 V, FRF = 250 MHz, FIF = 26 MHz
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AD6459
70 VGAIN = 0.2V 60
0.6 1 0.8
IF AMP/DEMOD GAIN - dB
50 VGAIN = 1.0V
ERROR - dB
0.4 0.2 0 -0.2 -0.4 -0.6 IF AMP/DEMOD MIXER
40 30 20
VGAIN = 1.5V
10 0
VGAIN = 2.25V 5 10 15 20 25 30 35 INTERMEDIATE FREQUENCY - dB 40 45
-0.8 -1.0 0 0.5 1 1.5 GAIN VOLTAGE - Volts 2 2.5
Figure 9. IF Amplifier and Demodulator Gain vs. Frequency, TA = +25C, VPOS = 2.7 V, VREF = 1.2 V
Figure 12. AD6459 Gain Error vs. Gain Control Voltage, Representative Part
12000
C SHUNT, VGAIN = 0.2V R SHUNT, VGAIN = 2.2V C SHUNT, VGAIN= 1.0V
3.5
3.0
QUADRATURE ERROR - Degrees
10000
3.0
2.5
CAPACITANCE - pF
RESISTANCE -
8000
2.5
2.0
6000
C SHUNT, VGAIN = 2.2V R SHUNT, VGAIN= 1.0V
2.0
1.5
4000
1.5
1.0
2000
R SHUNT, VGAINS= 0.2V
1.0
0.5
0 0 10 20 30 40 50 60 70 IF FREQUENCY - MHz 80 90
0.5 100
0
5
10
15
20 25 30 35 FREF FREQUENCY - MHz
40
45
Figure 10. IF Amplifier Input Impedance vs. Frequency, TA = +25C, VPOS = 2.7 V, VREF = 1.2 V
Figure 13. Demodulator Quadrature Error vs. FREF Frequency, TA = +25C, VPOS = 2.7 V
-5 -10 INPUT 1dB COMPRESSION POINT REFERED TO 50 - dBm -15
-90
-95
PHASE NOISE - dBc
-20 -25 -30 -35 -40 -45 -50 -55 0 0.5 1 1.5 GAIN VOLTAGE - Volts 2 2.5
-100
-105
-110
-115
-120 0.1
1
10 100 CARRIER FREQUENCY - kHz
1k
10k
Figure 11. IF Amplifier/Demodulator Input 1 dB Compression Point vs. VGAIN , FIF = 19.5 MHz, VREF = 1.2 V, TA = +25C, VPOS = 2.7 V
Figure 14. PLL Phase Noise vs. Frequency, VPOS = 3 V, C10 = 1 nF, FREF = 13 MHz
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-0.1 -0.3
FLTR PIN VOLTAGE REFERENCED TO VPOS - Volts
0 -10 -20 -30
-0.5
-0.7 -0.9 -1.1
INPUT IP3 REFERED TO 50 - dBm
-40 -50 -60
-1.3 -1.5 5 10 15 20 25 30 35 40 PLL FREQUENCY - MHz 45 50 55
-70
0.5
1.0 1.5 GAIN VOLTAGE - Volts
2.0
2.5
Figure 15. PLL Loop Voltage at FLTR Pin (KVCO) vs. Frequency
Figure 17. System (Mixer + IF LC Filter + I F Amplifier + Demodulator) IP3 vs. Gain, TA = +25C, VPOS = 2.7 V, IF = 13 MHz, VREF = 1.2 V
-10 -20
18 16 VPOS = 2.7V, TA = +85C
SUPPLY CURRENT - mA
INPUT 1dB COMPRESSION POINT REFERED TO 50 - dBm
-30
14 VPOS = 2.7V, TA = +25C 12 10 8 VPOS = 5.5V, TA = +25C 6 VPOS = 5.5V, TA = -40C 4 VPOS = 5.5V, TA = +85C
-40 -50 -60
-70 -80
0.5
1.0 1.5 GAIN VOLTAGE - Volts
2.0
2.5
0
0.5
1 1.5 GAIN VOLTAGE - Volts
2
2.5
Figure 16. System (Mixer + IF LC Filter +IF Amplifier + Demodulator) 1 dB Compression Point vs. Gain, TA = +25C, VPOS = 2.7 V, FIF = 13 MHz, VREF = 1.2 V
Figure 18. Power Supply Current vs. Gain Control Voltage, VREF = 1.2 V
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AD6459
PRODUCT OVERVIEW
The AD6459 provides most of the active circuitry required to realize a complete low power, single-conversion superheterodyne receiver, or the latter part of a double-conversion receiver, at input frequencies up to 500 MHz, with an IF from 5 MHz to 50 MHz. The internal I/Q demodulators, and their associated phase-locked loop, support a wide variety of modulation modes, including n-PSK, n-QAM and GMSK. A single positive supply voltage of 3 V is required (2.7 V minimum, 5.5 V maximum) at a typical supply current of 8 mA at midgain. In the following discussion, VPOS will be used to denote the power supply voltage, which will be normally assumed to be 3 V. Figure 20 shows the main sections of the AD6459. It consists of a variable-gain UHF mixer and a linear two-stage IF strip, which together provide a calibrated voltage-controlled gain range of more than 76 dB, followed by dual quadrature demodulators. These are driven by inphase and quadrature clocks that are generated by a Phase-Locked Loop (PLL), which is locked to a corrected external reference. A CMOS-compatible power-down interface completes the AD6459.
Mixer
mixer is determined, at the upper end, by the maximum input signal level of 90 mV (-11 dBm in 50 between RFHI and RFLO) up to which the mixer remains essentially linear, and at the lower end, by the noise level. It is customary to define the linearity of a mixer in terms of its 1 dB gain-compression point and third-order intercept, which for the AD6459 are -11 dBm and 0 dBm, respectively, in a 50 system. The mixer's RF input port is differential; that is, pin RFLO is functionally identical to RFHI, and these nodes are internally biased. The RF port can be modeled as a parallel RC circuit as shown in Figure 19.
RFHI CSH RFLO RSH
Figure 19. Mixer Port Modeled as a Parallel RC Network
The UHF mixer is an improved Gilbert-cell design and can operate from low frequencies (it is internally dc-coupled) up to an RF input of 500 MHz. The dynamic range at the input of the
The local oscillator (LO) input is internally biased at VP-0.8 V and must be ac coupled. The LO interface includes a preamplifier that minimizes the drive requirements, thus simplifying the oscillator design and reducing LO leakage from the RF port. The LO requires a single-sided drive of 50 mV, or -16 dBm in a 50 system. For operation above 300 MHz, noise figure can be improved by increasing the LO level.
LOIP 4 4.7k 17 IRXP 16 IRXN RFHI 6 MXOP 9 10 LC BANDPASS FILTER 11 12 IFIP + PLL - IFIM 50 4.7k 15 QRXP 14 QRXN 4.7k AGC VOLTAGE VPS1 20 VPS2 18 PRUP 3 2 COM1 7 COM2 BIAS CIRCUIT GAIN TO COMPENSATION 13 GAIN 19 FLTR 0 4.7k 1 FREF
RFLO 5
MXOM
AD6459
8 GREF
Figure 20. Functional Block Diagram
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The output of the mixer is differential. The nominal conversion gain is specified for operation into a 19.5 MHz LC IF bandpass filter as shown in Figure 21 and Table I. The conversion gain is measured between the mixer input and the input of this filter and varies between -5 dB and +15 dB.
C1 MXOP C2 L1 IFIP
Gain Scaling
The AD6459's overall gain, expressed in decibels, is linear with respect to the AGC voltage VGAIN at pin GAIN. The gain of all sections is maximum when VGAIN is 0.2 V and falls off as the bias is increased to VGAIN = 2.25 V. The gain is independent of the power supply voltage. The gain of all stages changes simultaneously. The AD6459's gain scaling is also temperature compensated. Note that GAIN pin of the AD6459 is an input driven by an external low impedance voltage source, normally a DAC, under the control of the radio's digital processor. The gain-control scaling is directly proportional to the reference voltage applied to the pin GREF and is independent of the power supply voltage. When this input is set to the nominal value of 1.2 V, the scale is nominally 27 mV/dB (37 dB/V). Under these conditions, 76 dB of gain range (mixer plus IF) corresponds to a control voltage of 0.2 V VGAIN 2.25 V. The final centering of this 2.05 V range depends on the insertion losses of the IF filters used. Pin GREF can be tied to an external voltage reference (VREF) provided, for example, by an AD1580 (1.21 V) voltage reference. When using the Analog Devices AD7013 (IS54, TETRA, and satellite receiver applications) and AD7015 or AD6421 (GSM, DCS1800, PCS1900) baseband converters, the external reference may also be provided by the reference output of the baseband converters. The interface between the AD6459 and the AD6421 baseband converter is shown in Figure 24. The AD7015 baseband converter provides a VR of 1.23 V. An auxiliary DAC in the AD7015 can be used to generate the AGC voltage. Since it uses the same reference voltage, the numerical input to this DAC provides an accurate RSSI value in digital form, no longer requiring the reference voltage to have high absolute accuracy.
AD6459
IRXP IRXN 100pF 100pF AD6421 IRXP IRXP
MXOM C1
IFIM
Figure 21. Suggested IF Filter Inserted Between the Mixer's Output Port and the Amplifier's Input Port
Table I. Filter Component Values for Selected Frequencies
Frequency 13 MHz 19.5 MHz 26 MHz 40 MHz
C1 27 pF 27 pF 22 pF 22 pF
L1 0.82 H 0.56 H 0.39 H 0.12 H
C2 180 pF 110 pF 82 pF 100 pF
The maximum permissible signal level between MXOP and MXOM is determined by the maximum gain control voltage. The mixer output port, having pull-up resistors of 250 to VPOS, is shown in Figure 22.
250 MXOP
VPOS 250 MXOM
Figure 22. Mixer Output Port
IF Amplifier
Most of the gain in the AD6459 is provided by the IF amplifier strip, which comprises two stages. Both are fully differential and each has a gain span of 26 dB for the AGC voltage range of 0.2 V to 2.25 V. Thus, in conjunction with the variable gain of the mixer, the total gain span is 76 dB. The overall IF gain varies from -13 dB to 45 dB for the nominal AGC voltage of 0.2 V to 2.25 V. Maximum gain is at VGAIN = 0.2 V. The IF input is differential, at IFIP and IFIM. Figure 23 shows a simplified schematic of the IF interface modeled as parallel RC network. The IF's small-signal bandwidth is approximately 50 MHz from IFIP and IFIM through the demodulator.
IFHI CSH IFLO RSH
QRXP QRXP 100pF 100pF
IRXP IRXN
GREF 0.1F 160 GAIN 1nF
BREFOUT BREFCAP
AGC DAC
FREF
VCTCXO
AFC DAC
Figure 23. IF Amplifier Port Modeled as a Parallel RC Network
Figure 24. Interfacing the AD6459 to the AD6421 Baseband Converter
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AD6459
I/Q Demodulators
Both demodulators (I and Q) receive their inputs internally from the IF amplifiers. Each demodulator comprises a full-wave synchronous detector followed by an 8 MHz, two-pole low-pass filter, producing differential outputs at pins IRXP and IRXN, and QRXP and QRXN. Using the I and Q demodulators for IFs above 50 MHz is precluded by the 5 MHz to 50 MHz range of the PLL used in the demodulator section. The I and Q outputs are differential and can swing up to 2.2 V p-p at the low supply voltage of 2.7 V. They are nominally centered at 1.5 V, independent of power supply. They can therefore directly drive the RX ADCs in the AD7015 baseband converter, which require an amplitude of 1.23 V to fully load them when driven by a differential signal. The conversion gain of the I and Q demodulators is 17 dB. For IFs of less than 8 MHz, the on-chip low-pass filters (8 MHz cutoff) do not adequately attenuate the IF or feedthrough products; thus, the maximum input voltage must be limited to allow sufficient headroom at the I and Q outputs for not only the desired baseband signal but also the unattenuated higherorder demodulation products. These products can be removed by an external low-pass filter. A simple 1-pole RC filter with its corner above the modulation bandwidth is sufficient to attenuate undesired outputs. The design of the RC filter is eased by the 4.7 k resistor integrated at each I and Q output pin.
Phase-Locked Loop
the VFQO always provides quadrature between its own I and Q outputs, but the phasing between it and the reference carrier will swing around the final value during the PLL's settling time.
Bias System
The AD6459 operates from a single supply (VPOS) usually 3 V, at a typical supply current of 8 mA at midgain and TA = +25C, corresponding to a power consumption of 24 mW. Any voltage from 2.7 V to 5.5 V may be used. The bias system includes a fast-acting active high CMOScompatible power-up switch, allowing the part to idle at 2 A when disabled. Biasing is generally proportional-to-absolutetemperature (PTAT) to ensure stable gain with temperature. Other special biasing techniques are used to ensure very accurate gain, stable over the full temperature range.
USING THE AD6459
In this section, we will focus on a few areas of special importance and include a few general application tips. As with any wideband high gain component, great care is needed in PC board layout. The location of the particular grounding points must be considered with due regard to the possibility of unwanted signal coupling. The high sensitivity of the AD6459 leads to the possibility that unwanted local EM signals may have an effect on the performance. During system development, carefully-shielded test assemblies should be used. The best solution is to use a fully enclosed box enclosing all components with the minimum number of needed signal connectors (RF, LO, I and Q outputs) in miniature coax form.
Gain Distribution
The demodulators are driven by quadrature signals that are provided by a variable-frequency quadrature oscillator (VFQO), phase-locked to a reference signal applied to pin FREF. When this signal is at the IF, inphase and quadrature baseband outputs are generated at the I output (IRXP and IRXN) and Q output (QRXP and QRXN), respectively. The quadrature accuracy of this VFQO is typically within 1.5 at 19.5 MHz. A simplified diagram of the FREF input is shown in Figure 25.
VPOS 5k 20k FREF 5k
As with all receivers, the most critical decisions in effectively using the AD6459 relate to the partitioning of gain between the various subsections (Mixer, IF Amplifier/Demodulator) and the placement of filters to achieve the highest overall signal-to-noise ratio and lowest intermodulation distortion. Figure 26 shows an example of the main RF/IF signal path at maximum and minimum signal levels.
SIGNAL LEVEL IN dBm -10 -15dBm -19dBm
50A PTAT
-20 -30 -40 -50 -60 -70 -80 -90 -100
-19dBm -22dBm
-16dBm -19dBm -36dBm
35mV
Figure 25. Simplified Schematic of the FREF interface
The VFQO operates from 5 MHz to 50 MHz and is controlled by the voltage between VPOS and FLTR. In normal operation a series RC network, forming the PLL loop filter, is connected from FLTR to VPOS. The use of an integral sample-hold system ensures that the frequency-control voltage on pin FLTR remains held during power-down, so reacquisition of the carrier occurs in less than 80 s. In practice, the probability of a phase mismatch at power-up is high, so the worst case linear settling period to full lock needs to be considered in making filter choices. This is typically < 80 s for a quadrature phase error of 3 at an IF of 19.5 MHz. Note that
-79dBm -95dBm -99dBm MIXER CONVERSION GAIN -82dBm
-76dBm -79dBm
3dB FILTER GAIN
IF GAIN
DEMOD. CONSTANT CONV. BASEBAND OUTPUT GAIN I Q
IF INPUT 250 MHz
Figure 26. Signal Levels and Gain, Showing 76 dB Typical and 80 dB Maximum Range in an Example Application
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AD6459
R1 20k C12 1nF 1 R9 50 LOIP R2 50 RFHI C3 SHORT R3 50 C7 1nF C2 1nF C4 1nF 2 3 4 5 6 7 8 GREF VPOS R6 24.9k R7 16.9k L4 SHORT C17 22pF C5 0.1F JUMPER FREF COM1 PRUP LOIP VPS1 20 R8 1k FLTR 19 VPS2 18 IRXP 17 IRXN 16 QRXP 15 QRXN 14 GAIN 13 IFIM 12 IFIP 11 C9 10nF C10 1nF C11 0.1F PRUP VPOS IRXP IRXN QRXP QRXN GAIN GREF VPOS C1 0.1F GND FREF
AD6459
RFLO RFHI COM2 GREF
9 MXOP 10 MXOM
L3 SHORT
C16 22pF
C15 110pF
L2 0.56H
Figure 27. Evaluation Board as Received with 19.5 MHz Filter
Table II. AD6459 Evaluation Board Input and Output Connection
Reference Designation RFHI LOIP FREF MXOP
Connector Type SMA SMA SMA SMA
Description RF Input LO Input Demodulator Reference Input Mixer Output
Coupling AC AC AC NA
Approximate Signal Level -11 dBm max 500 mV p-p max 100 mV p-p min NA
Comments Input Is Terminated in 50 Input Is Terminated in 50 Input Is Terminated in 50 Not Connected for Unbalanced Output Use XFMR Not Connected for Unbalanced Output Use XFMR Two Resistors Divider Gain Scaling Reference from External ADC Maw Gain at 0.2 V Z Series = 4.7 k Z Series = 4.7 k Z Series = 4.7 k Z Series = 4.7 k Supply Voltage If Left Unconnected, Board Is Active NA NA
IFIP
SMA
IF Input
NA
NA
J1 GREF GAIN QRXN QRXP IRXN IRXP VPOS PRUP GND GND
Jumper J2-1 J2-2 J2-3 J2-4 J2-5 J2-6 J2-7 J2-8 J2-J9 J2-10
On-Board GREF Bias External Reference Input Gain Bias Input Q-Negative Output Q-Positive Output I-Negative Output I-Positive Output Power Supply Positive Input Power Up Ground Ground
DC DC DC DC-2 MHz DC-2 MHz DC-2 MHz DC-2 MHz DC DC-2 MHz DC DC
0.4 VPOS 1.2 V dc 0.2 V to 2.4 V dc NA NA NA NA 2.7 V to 5.5 V CMOS 0V 0V
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AD6459
AD6459 EVALUATION BOARD Full Path Configuration
The AD6459 evaluation board (Figure 27) consists of a AD6459, ground plane, I/O connectors, and a 19.5 MHz band pass filter. The RF, LO and FREF ports are terminated in 50 to provide a broadband match or external signal generators. The board provides SMA connectors for the RF, LO, demodulator reference, mixer output and IF input signals. The MXOP and IFIP connectors are left unconnected and are provided as a testing convenience. Footprints for broadband matching transformers and matching components are also provided to aid in stage breakout testing. The remaining low frequency signals, including the I and Q interface, bias and power connections are made via a dual row pin header that acts as an Interface Connector located along the edges of the board. An on-board gain-reference 1.2 V biasing option is provided via a single jumper, J1. The evaluation board will not function without this jumper unless an external bias GREF is provided from an external reference that is normally provided by the associated ADC.
As received, the board is configured for full-path evaluation from RFHI to the I and Q outputs. The one-pole LC resonant circuit provided represents a simple, yet balanced, IF bandpass filtering approach. The filter supplied is centered at 19.5 MHz, a common GSM intermediate frequency. Table I highlights the filter component values for other IF frequencies. RFHI and RFLO are true differential inputs, however for testing convenience, the RFLO terminal of the AD6459 is ac referenced to ground on the evaluation board. The GAIN bias input, which is bypassed with a 10 nF capacitor, is brought out to the interface connector. The PRUP input is provided with a 20 k pull up resistor to VPOS that activates the board. The four differential I and Q outputs are brought out unconditioned, directly to the interface connector. A high impedance, high bandwidth FET-type probe should be used when measuring the I and Q ports. Excessive capacitive or resistive loading of these ports will severely limit the video bandwidth and signal swing. The demodulator PLL filter installed on the evaluation board (R8, C10) can accommodate the full VFQO lock range specified.
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.295 (7.50) 0.271 (6.90)
20
11
0.311 (7.9) 0.301 (7.64)
1
10
0.078 (1.98) PIN 1 0.068 (1.73)
0.07 (1.78) 0.066 (1.67)
0.212 (5.38) 0.205 (5.21)
0.008 (0.203) 0.002 (0.050)
0.0256 (0.65) BSC
SEATING 0.009 (0.229) PLANE 0.005 (0.127)
8 0
0.037 (0.94) 0.022 (0.559)
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PRINTED IN U.S.A.
C2204-12-10/96

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